Job Description: This is your opportunity to be involved in engineering implementation spec writing from marketing/system requirements, RTL design and verification, synthesis, and static timing analysis. You will be challenged with responsibility for block and/or chip level design and integration.
Job Requirements: BSEE plus 6+ years or MSEE 3+ years, or equivalent experience, developing, implementing, and testing high performance communications/networking ASIC products.
Experience in mapping communications algorithms or standards (for example Ethernet etc.) to hardware and understanding of system design tradeoffs for high volume applications.
Must have good RTL experience including specification, design, verification, and synthesis. Must have strong UNIX-based EDA tool skills and knowledge of ASIC design flows. Must be familiar with reusable HDL coding styles and design for high volume manufacture.
The candidate must have good personal communication skills, team working spirit, hardworking, and motivated to be part of a highly competent design team
Must be efficient in the following skills:
• Verilog/VHDL coding and Lint tools
• Synthesis using Synopsys tool suite
• Timing Analysis using Synopsys Primetime tool
• Formal Verification
• DFT concepts of Scan, BIST
• Strong Perl and Tcl scripting skill
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